Why Australian Enterprises Are Moving AI Inference On-Premises
Public cloud AI services have lowered the barrier to experimentation, but Australian enterprises running production inference workloads face a different calculation. Data sovereignty requirements under the Privacy Act 1988 and the Australian Privacy Principles mean that sensitive datasets — financial records, health information, government citizen data — often cannot leave Australian jurisdiction without significant compliance overhead. Latency matters too: inference calls that round-trip to offshore GPU regions add 50-150ms of delay per request, which compounds across real-time applications like fraud detection, clinical decision support, and manufacturing quality control.
Cost predictability is the third driver. Cloud GPU pricing for sustained inference workloads can exceed the total cost of ownership of equivalent on-premises hardware within 12-18 months, especially for models that run continuously rather than in burst patterns. A 2024 survey by IDC found that 67% of Asia-Pacific enterprises running AI workloads at scale were evaluating or deploying on-premises or collocated GPU infrastructure to control costs and latency.
For Australian organisations, the planning question is no longer whether to build private inference infrastructure, but how to design it correctly. This guide walks through the full stack — from GPU server selection through network fabric, optics, storage, and operations — with practical checkpoints for each decision.
Defining the Private Inference Stack: Servers, Fabric, Optics, and Storage
A private AI inference deployment is not a single product purchase. It is a system of four interdependent layers, and under-specifying any one layer creates bottlenecks that degrade the entire investment.
GPU Inference Servers form the compute layer. For inference (as distinct from training), the key metrics are memory bandwidth per dollar, model-serving throughput, and power efficiency. Inference servers typically pair one or two GPUs with high-capacity NVMe storage and 100G or 200G network interfaces. xSONIC AI Infrastructure Systems are designed for this tier, offering platforms optimised for private LLM serving, RAG pipelines, and multimodal inference workloads.
Network Fabric is the connective tissue. GPU inference servers must communicate with each other for distributed model serving and with storage for model weights and data retrieval. The fabric must deliver consistent, low-latency throughput without packet loss — a requirement that traditional over-subscribed leaf-spine designs struggle to meet at scale. SONiC-based data center switches running BGP and RDMA provide a standards-based, multi-vendor foundation for this layer. As the SONiC Foundation notes, SONiC is a Linux-based open source network operating system that runs on switches from multiple vendors and ASICs, offering a full suite of network functionality including BGP and RDMA that has been production-hardened in hyperscale data centers.
Optical Transceivers connect servers to leaf switches and leaf switches to spine switches. The choice of optics — SFP28 for 25G management, QSFP28 for 100G server links, QSFP-DD or OSFP for 400G/800G uplinks — must match the switch port density and cable plant of the facility. For Australian colocation sites, where cross-connect fees are per-link, using higher-density optics reduces both capex and recurring colocation charges.
NVMe Storage holds model weights, vector databases for RAG, and inference input/output buffers. PCIe Gen4 NVMe SSDs in U.2 or E1.S form factors provide the sequential read throughput needed to load multi-billion-parameter models into GPU memory without stalling. Storage latency directly affects time-to-first-token in inference pipelines.
The planning principle is simple: design the system, not the silo. A GPU server with insufficient network bandwidth wastes GPU cycles. A high-bandwidth fabric with undersized storage cannot feed models fast enough. Every layer must be sized in concert.
Designing the AI Fabric: Spine-Leaf Architecture for GPU Inference
The network fabric for a private inference cluster is typically a two-tier or three-tier spine-leaf topology. Each inference server connects to a leaf switch at 100G or 200G. Leaf switches uplink to spine switches at 400G or 800G. The number of spines determines the fabric’s east-west bandwidth and non-blocking ratio.
For inference workloads, the fabric has two distinct traffic patterns:
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Model-serving traffic between GPU servers running distributed inference (for example, tensor-parallel or pipeline-parallel model serving). This traffic is latency-sensitive and benefits from RDMA over Converged Ethernet (RoCE v2) transport.
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Data-plane traffic between inference servers and storage systems loading model weights, embeddings, and input data. This traffic is throughput-sensitive and benefits from high-bandwidth, non-blocking links.
SONiC-based switches support both traffic patterns natively. The SONiC architecture, as documented on the SONiC GitHub repository, uses a container-based modular design where each network function runs in its own Docker container. This provides fault isolation, simplified upgrades, and the flexibility to enable or disable features per deployment. SONiC supports BGP for underlay routing and RDMA for lossless Ethernet transport — both critical for AI fabric operation.
For Australian deployments, the xSONIC AI Fabric solution provides a reference architecture that maps switch selection, port density, and uplink ratios to common inference cluster sizes. A typical 16-GPU-server inference cluster, for example, might use two 400G leaf switches and two 400G spine switches, delivering 4:1 non-blocking oversubscription at full utilisation. Scaling to 64 or 128 GPU servers adds additional spines or moves to a three-tier architecture.
RoCE v2 and Lossless Ethernet: Making RDMA Work for Inference
RDMA over Converged Ethernet version 2 (RoCE v2) allows GPU servers to transfer data directly to and from remote memory without involving the CPU. For inference workloads that use tensor parallelism across multiple GPUs, RoCE v2 reduces inter-GPU communication latency by an order of magnitude compared to TCP/IP transport.
However, RoCE v2 requires a lossless Ethernet fabric. Packet loss on a RoCE v2 network triggers retransmissions that can stall GPU compute for milliseconds — catastrophic for real-time inference. Achieving lossless Ethernet requires three capabilities working together:
- Priority Flow Control (PFC): Pauses traffic on congested queues without dropping packets.
- Data Center Bridging Capability Exchange (DCBX): Negotiates QoS parameters between switches and servers automatically.
- Explicit Congestion Notification (ECN) and Congestion Notification Packets (CNPs): Signals congestion early so senders reduce rate before queues overflow.
SONiC supports all three mechanisms. NVIDIA’s Spectrum Ethernet switch line, which supports SONiC as one of its network operating system options alongside Cumulus Linux, provides hardware-accelerated RoCE v2 with zero-touch configuration on supported platforms. The xSONIC RoCE v2 solution guide and DCBX technology guide provide deployment playbooks for configuring lossless transport on SONiC-based fabrics.
For Australian enterprises, the practical question is whether their chosen inference framework supports RoCE v2. Major serving frameworks including vLLM, TensorRT-LLM, and Triton Inference Server can use NCCL and GDR (GPU Direct RDMA) for inter-GPU communication. If the inference deployment uses a single GPU server per model instance and does not require tensor parallelism, TCP transport may be sufficient and RoCE v2 configuration can be deferred.
The decision table below summarises when RoCE v2 is essential versus optional:
| Deployment Pattern | Transport Requirement | Notes |
|---|---|---|
| Single GPU, single server | TCP sufficient | No inter-GPU comm needed |
| Multi-GPU, single server (NVLink) | NVLink + TCP | GPU-to-GPU on same board |
| Multi-GPU, multi-server (tensor parallel) | RoCE v2 essential | Latency-sensitive cross-server GPU comm |
| Large model, pipeline parallel | RoCE v2 recommended | Reduces pipeline bubble time |
| RAG with remote vector DB | TCP or RoCE v2 | Depends on vector DB latency budget |
Optical Transceiver Planning for Inference Clusters
Optical transceivers are often an afterthought in AI infrastructure planning, but they are a significant cost line item and a common source of deployment delays. For a private inference cluster in an Australian colocation facility, the optics plan should address four link types:
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Server-to-leaf links: Typically 100G or 200G per server. SFP28 (25G) may be used for management interfaces. For 100G server links, QSFP28 SR4 (multimode, short reach up to 100m) or LR4 (single-mode, up to 10km) transceivers are standard choices.
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Leaf-to-spine uplinks: Typically 400G. QSFP-DD or OSFP form factors. SR8 (multimode) for intra-facility runs under 100m; DR4 or FR4 (single-mode) for longer runs or inter-building links.
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Spine-to-super-spine (three-tier): 400G or 800G. OSFP or next-generation form factors. These links often require single-mode optics for flexibility.
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Management and out-of-band: 1G or 10G SFP/SFP+ for switch management ports.
For Australian deployments, three practical considerations apply:
- Cross-connect costs: Many Australian colocation providers charge per cross-connect per month. Using higher-density optics (for example, 400G QSFP-DD instead of 4x 100G QSFP28) reduces the number of physical links and recurring cross-connect fees.
- Lead times: Specialty optics (800G OSFP, silicon photonics modules) may have longer lead times into Australia than commodity 100G/400G optics. Plan optics procurement at the same time as switch hardware, not after.
- Multi-vendor compatibility: SONiC’s multi-vendor support means optics from different manufacturers can be used, but firmware and DOM (digital optical monitoring) compatibility should be validated per switch platform.
xSONIC offers a range of optical transceivers across SFP, SFP+, SFP28, QSFP28, QSFP-DD, and OSFP form factors to match the link types above. The xSONIC Optical Transceiver product family is designed for compatibility with SONiC-based switches.
Related xSONiC Resources
Sources Reviewed
- The Wimbledon Public Ballot: https://www.wimbledon.com/en_GB/tickets/ballot
- Supports: input source for finding, recommendation, claim, and evidence review.
- SONiC Foundation: https://sonicfoundation.dev/
- Supports: input source for finding, recommendation, claim, and evidence review.
- SONiC GitHub: https://github.com/sonic-net/SONiC
- Supports: input source for finding, recommendation, claim, and evidence review.
- Azure SONiC Documentation: https://azure.github.io/SONiC
- Supports: input source for finding, recommendation, claim, and evidence review.
- Open Compute Networking: https://www.opencompute.org/projects/networking
- Supports: input source for finding, recommendation, claim, and evidence review.
- Broadcom Ethernet Switching: https://www.broadcom.com/products/ethernet-connectivity/switching
- Supports: input source for finding, recommendation, claim, and evidence review.
- Marvell Switching: https://www.marvell.com/products/switching.html
- Supports: input source for finding, recommendation, claim, and evidence review.
- NVIDIA Ethernet Switching: https://www.nvidia.com/en-us/networking/ethernet-switching
- Supports: input source for finding, recommendation, claim, and evidence review.